1. Field
The present disclosure relates to a signal level converter and a display driving device.
2. Description of the Related Art
A level shifter circuit converts an input signal at a lower voltage level into an output signal at a higher voltage level. An input transistor receiving the input signal is connected to a node to which a higher voltage is applied. For this reason, the input transistor includes a higher withstand voltage transistor to control breakdown.
The threshold voltage Vth of the higher voltage transistor is typically higher. A sufficient on-current is thus difficult to flow into the input transistor, and this makes it difficult for the input transistor to operate normally.
Japanese Unexamined Patent Application Publication No. 2012-33987 discloses a level shifter circuit that causes a higher voltage not to be applied to an input transistor while allowing a sufficient on-current to flow through the input transistor.
FIG. 12 illustrates a level shifter circuit 93 disclosed in Japanese Unexamined Patent Application Publication No. 2012-33987. The level shifter circuit 93 includes an N-type transistor T1 with the gate receiving an input signal IN at a lower power source voltage VDDL, an inverter INV that outputs an inverted signal of the input signal IN, an N-type transistor T2 with the gate thereof receiving the inverted signal output from the inverter INV, and P-type transistors T5 and T6.
The N-type transistors T1 and T2 are a lower withstand voltage N-type transistor or a medium withstand voltage N-type transistor, each having a lower threshold voltage Vth, and thus allows a sufficient on-current to flow. The gate of the higher withstand voltage P-type transistor T5 is connected to the drain of the higher withstand voltage P-type transistor T6. The gate of the higher withstand voltage P-type transistor T6 is connected to the drain of the higher withstand voltage P-type transistor T5.
In this specification, the lower withstand voltage N-type transistor or the medium withstand voltage N-type transistor may be referred to as a lower to medium withstand voltage N-type transistor. Let VDDL represent a withstand voltage of the lower to medium withstand voltage transistor, Vthl a threshold voltage of the lower to medium withstand voltage transistor, VDDH a withstand voltage of the higher withstand voltage transistor, and Vthh a threshold voltage of the higher withstand voltage transistor, and a relationship of VDDL<VDDH and Vthl<Vthh holds true.
If a lower or a lower to medium withstand voltage N-type transistor is used for each of the N-type transistors T1 and T2, a higher voltage may be applied to each of nodes C and D respectively connected to the N-type transistors T1 and T2. In order to alleviate a high voltage that may possibly be applied to the lower or lower to medium N-type transistors T1 and T2, a higher withstand voltage N-type transistor T3 is inserted between the N-type transistor T1 and the P-type transistor T5, and a higher withstand voltage N-type transistor T4 is inserted between the N-type transistor T2 and the P-type transistor T6.
A bias voltage VBIAS serving as an intermediate voltage is applied to the node of the gates of the higher withstand voltage N-type transistors T3 and T4 such that the node C and D do not reach a higher potential. In such a case, the output signal OUT of the level shifter circuit 93 is an output that is varied over a full amplitude from 0 V (ground voltage GND) to a higher power source voltage VDDH in response to the amplitude of the input signal IN.
The bias voltage VBIAS is generated by a bias generating circuit 92. The bias generating circuit 92 includes a N-type transistor T7 and a resistor R connected between the higher power source voltage VDDH and the ground voltage GND.
If variations occur in manufacturing process and in the higher power source voltage VDDH in the bias generating circuit 92 of FIG. 12, the bias voltage VBIAS varies. The on-current of the level shifter circuit 93 also varies.
If the bias voltage VBIAS decreases, the on-current of the level shifter circuit 93 is difficult to obtain, and the operation of the level shifter circuit 93 becomes unstable. On the other hand, if the bias voltage VBIAS increases, the on-current of the level shifter circuit 93 is obtained, but a higher voltage may be applied to the lower withstand voltage or lower to medium withstand voltage N-type transistors T1 and T2, possibly causing the N-type transistors T1 and T2 to break down or to be degraded.
As microfabrication of the lower or lower to medium withstand voltage transistors has advanced recently, the withstand voltage thereof decreases accordingly. Stable operation and reliability of a level shifter circuit are thus difficult to achieve. For this reason, an accurate bias voltage VBIAS is typically used. More specifically, the bias voltage VBIAS is set to be an optimum value In view of variations in a manufacturing process and an operation environment to provide the on-current of the level shifter circuit and to ensure reliability of the lower or lower to medium withstand voltage transistor. The bias generating circuit 92 of FIG. 12 is not suitable for generating such a bias voltage VBIAS.
A display driving device (integrated circuit) uses multiple voltage levels, such as a voltage for signal processing, a voltage for a display driving signal, and a voltage for a display gradation signal. For this reason, the display driving device typically uses multiple level shifter circuits. Since the display driving device outputs multiple display driving output signals, it has naturally an elongated shape.
The display driving device thus suffers from a difference in the ground voltage GND caused by wiring resistance, and variations in transistor characteristics due to heating caused in a circuit close to the level shifter circuit. Characteristics of the level shifter circuit vary depending on a wiring of the display driving device and a layout of the level shifter circuit respect to the circuit close thereto. The bias voltage VBIAS is to be generated in view of the environment where the level shifter circuit is mounted. Variations in the characteristics of the level shifter circuit may be improved by mounting the bias generating circuit close to the level shifter circuit. However, mounting the bias generating circuit on a dense layout region of the display driving device where multiple display output circuits are mounted leads to an increase in the layout area. Even if the level shifter circuit is mounted at a location part from the bias generating circuit, the bias voltage VBIAS in view of the variations in the characteristics of the level shifter circuit depending on the location of the layout is desirably generated without increasing the layout area.
It is desirable to provide a signal level converter and a display driving device that control an on-current of a level shifter circuit at a higher accuracy level.